The present invention relates generally to testing procedures for the semiconductor manufacturing process. More specifically, the present invention relates to alignment marks for measuring alignment error between different layers or different exposures on the same layer of a semiconductor wafer stack.
One of the most critical process control techniques used in the manufacturing of integrated circuits is the measurement of overlay accuracy between successive, patterned layers on a wafer. Overlay accuracy pertains to the determination of how accurately a patterned layer aligns with respect to the layer above or below it, or multiple exposures in the same layer.
Presently overlay measurements may be performed with test patterns that are printed onto the layers of a semiconductor wafer. As generally known, patterns may be printed onto semiconductor wafer layers through lithographic methods. Such methods generally involve applying a layer of photoresist material to a wafer layer, shining a light source through a patterned mask to expose certain areas of the photoresist, developing the exposed resist to produce the desired pattern of remaining resist, and then etching or implanting, etc. the surface of the wafer that is exposed through the photoresist. One type of test pattern for overlay measurement consists of sets of parallel patterns that are placed proximate to each other. The sets of parallel patterns formed on different wafer layers are positioned such that the a pattern from one set will align with a respective pattern from the other set when the layers are properly aligned. This test pattern and variations of this pattern are effective for determining the overlay error. However, inherent aspects of the lithographic processes and other semiconductor manufacturing processes limit the accuracy with which the test patterns may provide information as to the device overlay error. Optical lens aberrations of the lithography patterning equipment can cause pattern placement errors that are dependent on feature size, spacing, shape and location, and illumination conditions, including off-axis illumination and partial coherence. Other semiconductor manufacturing processes are also feature size dependent. It would be desirable to have overlay test patterns capable of improving the correlation between the overlay error measured on the test pattern and the real overlay error of the circuit components.
The present invention is directed towards alignment marks and methods for determining the overlay error between layers of a semiconductor wafer while minimizing measurement inaccuracies caused by semiconductor manufacturing processes. The present invention, in each of the various embodiments, uses alignment marks that are composed of periodic structures formed on each of two layers of a semiconductor wafer to provide alignment information between those two layers of the semiconductor device. The alignment marks are formed in specific locations on each wafer layer such that the alignment marks on one layer will be aligned with the mark on the other layer when the two layers are properly aligned. It follows that when the two layers are properly aligned, it is more likely that the integrated circuit patterns on the two layers will be aligned. Therefore, the degree of alignment between the circuit patterns on each wafer layer may be determined by measuring the alignment between the marks on each layer.
One aspect. of the invention pertains to an alignment mark for measuring the relative position between different layers of a semiconductor device. The alignment mark includes a first test zone and a second test zone. The first test zone includes two sections, one in which test structures are formed on one layer and a second in which test structures are formed on a second layer. Each of these test structures are composed of smaller sub-structures. The second test zone includes two similar sections that are also composed of smaller sub-structures. By forming each of these test structures with sub-structures that are sized closer to the size of the actual circuits, a more accurate measurement of any alignment error in such circuits is obtained. The first and second test zones are configured so that the section of each test zone formed in one layer is adjacent to the section of the other test zone which is formed on the other layer. Another aspect of the present invention pertains to a method of utilizing the alignment mark so that an overlay measurement may be obtained.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.